Magnetoresistive random access memory (MRAM) is a non-volatile memory technology that stores data through magnetic storage elements. The elements are two ferromagnetic plates or electrodes that can hold a magnetic field and are separated by a non-magnetic material, such as a non-magnetic metal or insulator. This structure is known as a magnetic tunnel junction (MTJ). MRAM devices are considered to be a next generation structure for a wide range of memory applications.
FIG. 1 illustrates an example of an MRAM cell 110 including an MTJ 120. In general, one of the plates (a reference layer or fixed layer 130) has its magnetization pinned, meaning that this layer has a higher coercivity than the other layer and requires a larger magnetic field or spin-polarized current to change the orientation of its magnetization. The second plate is typically referred to as the free layer 140 and its magnetization direction can be changed by a smaller magnetic field or spin-polarized current relative to that of the reference layer 130. The two plates can be sub-micron in lateral size, and the magnetization direction can still be stable with respect to thermal fluctuations.
MRAM devices can store information by changing the orientation of the magnetization of the free layer 140. In particular, based on whether the free layer 140 is in a parallel or anti-parallel alignment relative to the reference layer 130, either a binary value of “1” or a binary value of “0” can be stored in the MRAM cell 110 as represented in FIG. 1.
MRAM products based on spin transfer torque switching, or spin transfer switching, are already making their way into larger data storage devices. Spin transfer torque MRAM (STT-MRAM) devices, such as the one illustrated in FIG. 1, use spin-aligned (polarized) electrons to change the magnetization orientation of the free layer in the magnetic tunnel junction. In general, electrons possess a quantized number of angular momentum intrinsic to the electron referred to as spin. An electrical current is generally unpolarized; that is, it consists of 50% spin-up and 50% spin-down electrons. By passing a current though a magnetic layer, electrons are polarized with a spin orientation corresponding to the magnetization direction of the magnetic layer (e.g., polarizer), thereby producing a spin-polarized current. If the spin-polarized current is passed to the magnetic region of the free layer 140 in the MTJ device, the electrons will transfer a portion of their spin-angular momentum to the magnetization layer to produce a torque on the magnetization of the free layer. This spin transfer torque can switch the magnetization of the free layer 140, which in effect writes either a “1” or a “0” based on whether the free layer is in the parallel or anti-parallel state relative to the reference layer 130.
Due to the spin-polarized electron tunneling effect, the electrical resistance of the cell changes due to the orientation of the magnetic fields of the two layers 130 and 140. The electrical resistance is typically referred to as tunnel magnetoresistance (TMR), which is a magnetoresistance effect that occurs in an MTJ. The cell's resistance will be different for the parallel and anti-parallel states, and thus the cell's resistance can be used to distinguish between a “1” and a “0.”
Generally speaking, to read a memory cell, a current is applied to the bit line that includes that cell (the “main bit line”) to detect the value of the cell's resistance by monitoring the voltage across the cell. A sense amplifier is used to sense the voltage level on the main bit line and compare it to a reference bit line voltage. The reference bit line voltage is established at a level that is between the main bit line voltage that corresponds to a bit value of 1 and the main bit line voltage that corresponds to a bit value of 0. If the main bit line voltage is greater than the reference bit line voltage, then a “1” is stored in the cell; and if the main bit line voltage is less than the reference bit line voltage, then a “0” is stored in the cell.
There is a sense amplifier for each bit line. Thus, for example, for a 32-bit read, 32 sense amplifiers are used. Ideally, the sense amplifiers would be identical, but often there is a mismatch between them due to variations in circuit parameters deriving from manufacturing process, layout, position in the memory array, and location of the ground. These mismatches can result in erroneous reads.
This problem is illustrated by the example of FIGS. 2A and 2B. A reference bit line bias transistor 211 is connected to the reference bit line 201, and a main bit line bias transistor 212 is connected to the main bit line 202 of a memory cell being read. As illustrated in FIG. 2B, during the clock period of the sense amplifier 220, the reference bit line voltage supplied to the sense amplifier (Vs) is less than both the voltage (V1) that corresponds to a bit value of 1 and the voltage (V0) that corresponds to a bit value of 0 due to circuit parameter mismatch between the main bit line and the reference bit line. Thus, regardless of the actual bit value (0 or 1) stored by the memory cell that is being read, the sense amplifier 220 will sense a bit value of 1. That is, even if the actual stored bit value is 0, the sense amplifier 220 may erroneously sense a bit value of 1.
In an MTJ device, the difference between the main bit line voltage corresponding to a “1” and that corresponding to a “0” (the sensing margin) is small because the bit line resistance in series reduces the resistance ratio of the MTJs as seen by the sense amplifier. Also, a bias across an MTJ reduces the MTJ's resistance, especially the resistance of the anti-parallel state, and so TMR is reduced relative to the case of zero bias. Reduced TMR further decreases the sensing margin, which increases the possibility of an erroneous read. Thus, because of the relatively small sensing margin in MTJ devices, the problem of mismatches due to variations in circuit parameters and reference bit line voltage is particularly acute.